To save precious layout space or increase interconnect efficiency, multiple chips of integrated circuits (ICs) can be stacked together as a single IC package. To that end, a three-dimensional (3D) stack packaging technology is used to package the chips of integrated circuits. Through-silicon vias (TSVs) are widely used to accomplish the 3D stack packaging technology. A through-silicon via is a vertical conductive via completely passing through a silicon wafer, a silicon board, a substrate of any material or die. Nowadays, a 3D integrated circuit (3D IC) is applied to a lot of fields such as memory stacks, image sensors or the like.
Although through-silicon vias comes with a lot of advantages, they also introduce some issues into 3D IC architecture such as thermal mismatch, mechanical stress, heat dissipation etc. Nowadays, all the electronic devices are expected to be small, so extra heat generated by through-silicon vias would be a problem if it accumulates within the chip. Therefore, there is a need to propose an improved heat dissipating approach.